As a capacitor that is formed in accordance with semiconductor processes, a MIM capacitor has some advantages over other structures, such as a MIS (Metal-Insulator-Silicon) capacitor. The advantages include that the accuracy of the capacitance can be increased, and the chip area can be made small because the capacitor can be formed in the upper wiring layer. Thus, it is anticipated that the MIM capacitor is used in a wide variety of ways, such as CMOS, BiCMOS, and bipolar chips. Typical uses of the MIM capacitor include: a filter or an analog capacitor in an A/D or D/A converter, an oscillator or oscillation circuit in an RF circuit, an RF coupling and a capacitor for RF device in a matching network.
In a high accuracy A/D converter, it is required that the capacitance variation of the capacitance be very small. Note that this capacitance variation occurs depending on a voltage to be applied to the capacitor or the temperature. However, it is difficult to realize those characteristics required for the capacitor, using only a MIM capacitor device. In general, to compensate for the capacitance variation, a compensating circuit is provided. If the MIM capacitor capacitance depends only a little on the voltage or temperature, the compensating circuit is not necessary, and the chip area can be reduced.
Capacitance “C” of the MIM capacitor has a relationship with a voltage V to be applied to the capacitor. The relationship can be expressed by an equation, C=CV(0)+CV(1)·V+CV(2)·V2, when CV(0) is the capacitance density at 0 V, CV(1) is the linear voltage coefficient of capacitance, and CV(2) is the quadratic voltage coefficient of capacitance. The voltage secondary coefficient CV(2) differs depending on the material of the insulating film included in the capacitor. In the case of a P—SiN film as a silicon nitride film in accordance with an insulating film plasma CVD technique, the voltage secondary coefficient CV(2) may be in a range from +25 to +40 ppm/V2. Similarly, in the case of a P—SiO film as a silicon oxide film in accordance with the plasma CVD technique, the voltage secondary coefficient CV(2) may be in a range from −25 to −35 ppm/V2.
Non-patent document 1 (Thanh Hoa Phung, et al., “Modeling the Negative Quadratic VCC of SiO2 in MIM capacitor”, IEEE ELECTRON DEVICE LETTERS, VOL 32, NO. 12, PP 16 71-1673, DECEMBER 2011) considers that the voltage secondary coefficient is generated due to the polarization in the CVD film. In this document, it is discussed that, in the case of a SiO film, the film defects are reduced by performing annealing treatment, thereby decreasing the voltage secondary coefficient CV(2) (Non-patent document 1 (Thank Hoa Phung, et al., “Modeling the Negative Quadratic VCC of SiO2 in MIM capacitor”, IEEE ELECTRON DEVICE LETTERS, VOL 32, NO. 12, PP 16 71-1673, DECEMBER 2011)). In addition, it is estimated that the polarization is caused by the orientation polarization due to the film defects.
Non-patent document 2 (S. Van Huylenbroeck, et al, “A 0.25 μm SiGe BiCMOS Technology including Integrated RF Passive Components optimized for Low Power Applications”, European Solid-State Device Research, 2003 33rd Conference on. ESSDERC '03, pp. 506-508, 2003), discloses a technique for canceling positive/negative coefficients by forming the insulating film with a bilayer structure of SiO/SiN, by focusing on a point that the SiN film and the SiO film have a positive or negative voltage secondary coefficient (FIG. 9 Non-patent document 2).
Like Non-patent document 2 (S. Van Huylenbroeck, et al, “A 0.25 μm SiGe BiCMOS Technology including Integrated RF Passive Components optimized for Low Power Applications”, European Solid-State Device Research, 2003 33rd Conference on. ESSDERC '03, pp. 506-508, 2003), Patent document 1 (Japanese Unexamined Patent Application Publication No. 2002-151649) focuses on that the P—SiN film has positive voltage dependency and the P—SiO film has negative voltage dependency. Further, Patent document 1 (Japanese Unexamined Patent Application Publication No. 2002-151649) discloses a technique for canceling the voltage dependency by connecting a MIM capacitor with the P—SiN film as an insulating film and a MIM capacitor with the P—SiO film as an insulating film, through a circuit.
Patent document 2 (Japanese Unexamined Patent Application Publication No. 2006-173319) discloses a MIM capacitor with a SiON film as an insulating film, and discloses a technique for attaining a MIM capacitor whose capacitance has low voltage dependency.